1. Field of the Invention
This invention relates generally to devices utilizing memories with repair capabilities, and more particularly to a method for substantially removing system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology.
2. Description of the Prior Art
Devices utilizing memories with repair capability require an E-fuse farm module be included on the device chip. The E-fuse farm contains the programmable fuse elements for storing the repair information as well as the control logic for programming and loading the repair information into the memories. The repair information is loaded into the memories from the E-fuse farm module upon device power-up via a serial scan chain path connecting the E-fuse farm and the memories. Once the repair information has been scanned into the memories, the E-fuse farm logic performs no additional functions and remains idle. In current implementations, power must be maintained to all memories in the device and the E-fuse farm module. One current E-fuse farm implementation is illustrated in FIG. 1 that depicts a plurality of SRAM memory devices 10, 12, 14, 16, each containing its distinct set of repair data registers 18, 20, 22, 24, connected to an E-fuse farm 26. If power is cut to one or more memories 10, 12, 14, 16 and/or the E-fuse farm 26, the repair information will be lost and access to the memories will not be possible until the device is powered off and then on again to reload the repair data. Current implementations thus provide no methodology to power down one or more memories for low power/leakage applications.
In view of the foregoing, it would be both beneficial and advantageous to provide a method for substantially removing system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology.